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az displays, inc. part numbe r: AGM1064B series revised: may 14, 2003 complete lcd solutions specifications for liquid crystal display
page 1 general specification table 1 item standard value unit character format 100x64 dots dots module dimension 34.1(w) *25.3(h) *2.0(t) mm viewing area 28.0(w) * 20.9(h) mm dot size 0.21(w) * 0.234(h) mm dot pitch 0.24(w) * 0.264(h) mm driving 1/64duty, 1/9bias view direction 6h ?? 12h ?? other: ?? lcd type tn ?? stn gray ?? stn blue ?? stn yellow green ?? fstn positive ?? fstn negative ?? color stn ?? fm lcd ?? display mode reflective ?? transflective?? transmissive ?? driver ic nt7532h - tabf1 interface 6800 ?? 8080?? ? 2 ??? dc/dc converter interna l ?? external ?? operation temperature - 10???a60?? storage temperature - 20???a70??
page 2 electronic units 3.1 absolute maximum rating s no item symbol min. t yp . max. unit 1 operating temperature t op -10 - 60 ?? 2 storage temperature t st -20 - 70 ?? 3 supply voltage for logic v dd -v ss vss 3.6 v 4 supply voltage for lcd v lcd v ss 13.5 v 5 input voltage v i vss - vdd+0.5 v 6 static electricity be sure that you are grounded when handing lcm 3.2 electrical characteristics (ta=25??, v dd =3.0v ) no item symbol condition min . t yp . max. uni t 1 supply voltage for logic v dd - v ss / / 3.0 / v 2 supply voltage for l cd driver v dd - v o (v lcd ) / / 10.0 / v 3 input high voltage v ih h level 0.8 v dd / v dd v 4 input low voltage v il l level 0 / 0.2v dd v 5 supply current for logic i dd / / / 1 ma 9 used ic nt7532h-tabf1(novatek) *idd measureme nt condition is for all pixels on display. (unit: ma)
page 3 3 .3 interface pin function table 5 no symbol i/o description 1 nc 2 nc 3 nc 4 nc 5 fr i/o this is the liquid crystal alternating current signal i/o termin al m/s = ?h?: output m/s = ?h?: input when the nt7532 chip is used in master/slave mode, the various fr terminals must be connected. 6 cl i/o this is the display clock input terminal. when the nt7532 chips are used in master/slave mode, the various cl ter minals must be connected. 7 /dof i/o this is the liquid crystal display blanking control terminal. m/s = ?h?: output m/s = ?h?: input when the nt7532 chip is used in master/slave mode, the various dof terminals must be connected. 8 nc nc 9 /cs1 10 cs2 i this is the chip select signal. when cs1=?l? and cs2=?h?, then the chip select becomes active, and data/command i/o is enabled. 11 res i when res is set to ?l?, the settings are initialized. the reset operation is performed by the res signal level 1 2 a0 i this is connected to the least significant bit of the normal mpu address bus, and it determines whether the data bits are data or a command. a0 = ?h?: indicate that d0 to d7 are display data a0 = ?l?: indicates that d0 to d7 are control data 13 rd/ wr i when connected to an 8080 mpu, this is active low. this terminal connects to the 8080 mpu wr signal. the signals on the data bus are latched at the rising edge of the wr signal. when connected to a 6800 series mpu, this is the read/write control signa l input terminal. when w r/ = ?h?: read when w r/ = ?l?: write 14 e/rd i when connected to an 8080 mpu, it is active low. this pad is connected to the rd signal of the 8080mpu, and the nt7532 data bus is in an output status when this signal is ?l?. when c onnected to a 6800 series mpu, this is active high. this is used as an enable clock input of the 6800 series mpu 15 d0 i/o this is an 8 - bit bi - directional data bus that connects to an 8 - bit or 16 - bit standard mpu data bus.
page 4 16 d1 17 d2 18 d3 19 d4 20 d5 21 d6?scl ? 22 d7?si? when the serial interface is selected (p/s=?l?), then d7 serves as the serial data input terminal (si) and d6 serves as the serial clock input terminal (scl). at this time, d0 to d5 are set to high impedance. when the chip select is inactive, d0 to d7 are set to high impedance. 23 duty0 24 duty1 i select the lcd driver duty duty1 duty1 lcd driver duty 0 0 1/33 0 1 1/49 1 0 1/55 1 1 1/69 25 vdd supply 2.4 - 3.5v power supply input. these pads must be connect ed each other. 26 vdd2 supply this is the power supply for the step-up voltage circuit for the lcd. these pads must be connected each other. 27 vss supply ground output for pad option. 28 vout o dc/dc voltage converter output 29 nc nc 30 cap3+ o capacitor 3+ pad for internal dc/dc voltage converter. 31 cap1 - o capacitor 1- pad for internal dc/dc voltage converter. 32 cap1+ o capacitor 1+ pad for internal dc/dc voltage converter. 33 cap2+ o capacitor 2+ pad for internal dc/dc voltage converter. 34 cap2 - o capacitor 2- pad for internal dc/dc voltage converter. 35 vext i this is the external input reference voltage (vref) for the internal voltage regulator. it is valid only when external vref is used. vext must be 3 2.4v and vdd2. when using internal vref, this pad must be nc.
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page 7page 6 voltage divider attached to the vr terminal. this pad is enabled only when the master operation mode is selected. it is fixed to either ?h? or ?l? when the slave operation mode is selected 49 nc nc 3. 4 commands the display control instructions control the internal state of the nt7532h -tabf1(novatek) . instruction is received from mpu to nt7532h -tabf1(novatek) for the splay control. the following table shows various instructions. *: don?t care code command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex function display off 0 1 0 1 0 1 0 1 1 1 0 1 aeh afh turn on lcd panel when goes high, and turn off when goes low set display start lin e 0 1 0 0 1 display start address 40h to 7fh specifies ram display line for com0 set page address 0 1 0 1 0 1 1 page address b0h to bfh set the display data ram page in page address register 0 1 0 0 0 0 1 higher column address set column address 0 1 0 0 0 0 0 lower column address 00h to 1fh set 4 higher bits and 4 lower bits of column address of display data ram in register read status 0 0 1 status 0 0 0 0 xx reads the status information write display data 1 1 0 write data xx write data in display data ram read display data 1 0 1 read data xx read data from display data ram adc select 0 1 0 1 0 1 0 0 0 0 0 1 a0h a1h set the display data ram address seg output correspondence normal/rever se display 0 1 0 1 0 1 0 0 1 1 0 1 a6h a7h normal indication when low, but full indication when high entire display on/off 0 1 0 1 0 1 0 0 1 0 0 1 a4h a5h selects normal display (0) or entire display on set lcd bias 0 1 0 1 0 1 0 0 0 1 01 a2h a3h sets lcd driving voltage bias ratio read -modify- write 0 1 0 1 1 1 0 0 0 0 0 e0h increments column address counter during each write end 0 1 0 1 1 1 0 1 1 1 0 eeh releases the read-modify-write
page 5 reset 0 1 0 1 1 1 0 0 0 1 0 e2h resets internal functions common output mode selec t 0 1 0 1 1 0 0 0 1 * * * c0h to cfh selects com output scan direction *: invalid data set power control 0 1 0 0 0 1 0 1 operation status 28h to 2fh selects the power circuit operation mode v0 voltage regulator internal resistor ratio set 0 1 0 0 0 1 0 0 resistor ratio 20h to 27h selects internal resistor ratio rb/ra mode 0 1 0 1 0 0 0 0 0 0 1 81h electronic volume mode set electronic volume register set 0 1 0 * * electronic control value xx sets the v0 output voltage electronic volume register 0 1 0 0 0 1 0 1 0 1 0 1 ach adh sets static indicator on/off 0: off, 1: on set static indicator on/off set static indicator register 0 1 0 * * * * * * mode xx sets the flash mode power save 0 1 0 - - - - - - - - - compound command of display off and entire display on nop 0 1 0 1 1 1 0 0 0 1 1 e3h command for non-operation test command 0 1 0 1 1 1 1 * * * * f1h to ffh ic test command. do not use! test mode reset 0 1 0 1 1 1 1 0 0 0 0 f0h command of test mode reset
page 5 3. 5 timing characteristics 1. system buses read/write characteristics (for 8080 series mpu) symbol parameter min typ max unit condition t ah8 address hold time 0 - - ns t as 8 address setup time 0 - - ns a0 t cyc 8 system cycle time 300 - - ns scl t ewhw control low pulse width (write) 90 - - ns wr t ewhr control low pulse width (read) 120 - - ns rd t ewlw control high pulse width (write) 120 - - ns wr t ewlr control high pulse width (read) 60 - - ns rd t ds 8 data setup time 40 - - ns t dh8 data hold time 15 - - ns d0~d7 t acc8 /rd access time - - 140 ns t oh8 output disable time 10 - 400 ns d0~d7, cl = 100pf *1. the input signal rise time and fall time (t r , t f ) is specified at 15ns or less. (t r + t f ) < (t cyc8 - t cclw - t cchw ) for write, (t r + t f ) < (t cyc8 - t cclr - t cchr ) for read. *2. all timing is specified using 20% and 80% of vdd as the reference. *3. t cclw and t cclr are specified as the overlap interval when cs1 is low (cs2 is high) and wr or rd is low. 2. system buses read/write characteristics (for 6800 series mpu)
page 5 symbol parameter min typ max unit condition t ah6 address hold time 0 - - ns t as6 address setup time 0 - - ns a0 t cyc6 system cycle time 300 - - ns scl t ewhw control low pulse width (write) 90 - - ns wr t ewhr control low pulse width (read) 120 - - ns rd t ewlw control high pulse width (write) 120 - - ns wr t ewlr control high pulse width (read) 60 - - ns rd t ds6 data setup time 40 - - ns t dh6 data hold time 15 - - ns d0~d7 t acc6 /rd access time - - 140 ns t oh6 output disable time 10 - 400 ns d0~d7, cl = 100pf
page 5 3. serial interface timing symbol parameter min typ max unit condition t scyc serial clock cycle 250 - - ns scl t shw serial clock h pulse width 100 - - ns scl t slw serial clock l pulse width 100 - - ns scl t sas address setup time 150 - - ns d/i t sah address hold time 150 - - ns d/i t sds data setup time 100 - - ns sdi t sdh data hold time 100 - - ns sdi t css chip select setup time 150 - - ns cs1, cs2 t csh chip select hold time 150 - - ns cs1, cs2 *1. the input signal rise time and fall time (tr, tf) is specified at 15ns or less. *2. all timing is specified using 20% and 80% of vdd as the standard.
page 5 electro -optical units 4.1 electro - optical characteristics no item symbol condition min typ max unit drive 1 contrast ratio c r - 5. 5 - - rise t r - 260 - m s 2 response time down t f t a = 2 3 3 ?? | 1 =| 2 = | 3 =| 4 =0 - 200 - m s 6h |?=270 | 1 - 60 - 12h |?=90 | 2 - 25 - 3h |?=0 | 3 - 50 - 3 viewing angle range 9h |?=180 | 4 t a = 23 3 ?? c r =2 - 50 - deg v op =10v 1/64 duty 1/9 bias f=100h z 4 lcd driving voltage v op t a = 23 3 ?? - 10 - v
blue anode 3.vdd=3.0v vlcd=10.0v 6.driver ic:nt7532h-tabf1 1.mode: fstn-transflective-positive 7.the tolerance unless classified ?0.2 2.1/65duty,1/9bias,view angle 6 o'clock 4.operation temperature:-10??c~+60??c 5.store temperature:-20??c~+70??c d wg: sm5424 a gm1064b-mlb-fb w az d ispla y s , inc .

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